Contents

• 1. Hardware Description Language

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  Introduction, HDL (Hardware Description Language), HDL for Digital Logic Design, HDL Design Flow Process, VHDL, Use of Hardware Description Languages in Digital Logic Design, Features of VHDL, Modeling Concepts, Level of Representation and Abstraction, Basic Structure of VHDL File, Library and Packages, Entity Declaration, Architecture Body, Lexical Elements and Syntax, Identifiers, Keywords (Reserved Words), Numbers, Special Symbols, Characters, Strings and Bit Strings, Comments, Syntax Description, Data Objects: Signals, Variables and Constants, Constant, Variable, Signals, Data Type, Scalar Type, Composite Type, Access Type, File Type, Sub Type, Operators, Basic Modeling Construct, Dataflow Style Modeling, Behavioral Modeling, Structured Modeling, Sequential Statement, Case Study for Ripple Carry Adder, Case Study For Look Ahead Carry Adder, Review Questions.
   
  2. VHDL

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  Introduction, Process, Sub Programs, Procedures, Functions, Packages, Package Declaration, Package Body, Use Clauses, Aliases, Resolved Signals, Resolution Function for Three-State Logic, Resolution of Processes, Components, Configurations, Generate Statements, Concurrent Signal Assignment Statements, Conditional Signal Assignment, Selected Signal Assignment, Use of VHDL in Digital System Simulation and Synthesis, Simulation, Test Bench, Synthesis, Review Questions.
   
  3. Clock-Driven Sequential Circuits

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  Introduction, Sequential Logic Circuits, Analysis of a Clocked Sequential Circuit, Design Steps for Synchronous Sequential Circuits, The Design of a Sequence Detector, The Moore and Mealy State Machines, Design using JK Flip-Flops and D Flip-Flops, State Reduction, State Assignment, Algorithmic State Machine Charts, Conversion of an ASM Chart into Hardware, Considerations of Clock Skew, Parameters of Flip-Flops, Clock Timing Constraints, Read Only Memory (ROM), Boolean Function Implementation Through ROM, Programmable Logic Device (PLD), Programmable Grid Array (PGA), Programmable Logic Array (PLA), Programmable Array Logic (PAL), Field Programmable Gate Array (FPGA), Review Questions.
   
  4. Event Driven Circuits

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  Introduction, Design Procedure for Asynchronous Circuit, Stable and Unstable States, Races, Race free Assignments, State Reduction for Incompletely Specified Machines, Compatibility, Determination of Compatible Pairs, Merger Diagram, The State Reduction Procedure, Review Questions.
   
  5. Hazards

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  Introduction, Hazards, The Generation of Static Hazards in Combinational Networks, Dynamic Hazards, Function Hazards, Essential Hazards, Designing of Hazard-free Combinational Networks, Eliminating Hazard, Review Questions.
   
  6. Introduction to FPGAs

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  Introduction, Field Programmable Gate Arrays, Logic Blocks for FPGAs, The Interconnect, Design Process of FPGA-Based Circuit, Extended Logic Elements, Static Memory Programming Technology, Antifuse Programming Technology, SRAM vs. Antifuse Programming, EPROM, EEPROM, and FLASH Memory Programming, Case Study of Altera Stratix FPGAs, Case Study of Xilinx Virtex-II Pro, Technology Mapping, Logic Synthesis, LUT-Based Technology Mapping, Review Questions.
   
  P. Papers