Contents

• Unit I INTRODUCTION: VHDL/PLD Design Methodology, Advantages, Requirement Analysis and specification, VHDL description, Verification Using simulations, Functional Simulation, Logic Synthesis, Place and route and timing Simulation Fundamental & history of various hardware description language, VHDL for Synthesis V/s Simulation, Design flow of ASICs and standard logic circuits. Implementation Details for SPLDs, CPLDs and FPGAs.

  Unit II LANGUAGE FUNDAMENTALS: Entities, Architectures and coding Styles, Signals and Data types, Packages, Dataflow, Structural, Behavioral and RTL Style of Combinational design, Event- Driven Simulation: Simulation Approaches, Elaboration Signal Drivers Simulator Kernel process, Signals verses Variables.

  Unit III COMBINATIONAL and SEQUENCIAL CIRCUITS BUILDING BLOCKS: Multiplexer, Synthesis using Shannon’s expansions, Decoders, encoders, Code Converters, VHDL Code for Combinational Circuits. VHDL code for Flip-Flops, shift registers, Counters.

  Unit IV SYNCHRONOUS/ ASYNCHRONOUS SEQUENCIAL CIRCUITS: Mealy & Moore type FSMs, VHDL Code for Mealy & Moore Machines, VHDL Codes for Serial Adder, Vending Machine.

  Unit V DIGITAL SYSTEM DESIGN: Building Block circuits, Memory organization, SRAM, Design examples of divider, Multiplier, Shifting & Sorting Operations, Clock Synchronization, CPU organization and design concepts.