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Specifications of VHDL

Book Details

  • 978-93-80311-64-7
  • English
  • 2012, 2013, 2014
  • Paper Back
  • -


  • 1. Introduction
    Objectives, Fundamental and History of Various Hardware Description Languages, History, Designing of HDL, Why VHDL, HDL Code Simulation, Design Constraints of HDLs, HDL as a Programming Languages, Example, VHDL as a Programming Language, Lexical Elements, Data Types and Objects, Expressions and Operators, Sequential Statements, Subprograms and Packages, VHDL Description of Structure, Entity Declarations, Architecture Declarations, VHDL Description of Behaviour, Signal Assignment, Processes and The Wait Statement, Concurrent Signal Assignment Statements, Model Organization, Design Units and Libraries, Configurations, Design Examples, Advanced VHDL, Signal Resolution and Buses, Null Transactions, Generate Statements, Concurrent Assertions and Procedure Calls, Entity Statements, Design Flow of ASICs, Advantages, Types of ASICs, Full-Custom ASICs, Standard-Cell-Based ASICs, Gate-Array-Based ASICs, Channeled Gate Array, Channel Less Gate Array, Structured Gate Array, Programmable Logic Devices, Field-Programmable Gate Arrays, Design Flow, Synthesizeable Constructs and VHDL Templates, Some Examples of Synthesizable Code Follow Below, Summary, Review Questions.
    2. Combinational Circuit Building Blocks
    Objectives, Combinational Logic Blocks, Data Selector or Multiplexers, Synthesis of Logic Functions using Multiplexers, Multiplexer Synthesis using Shannon’s Expansion, Decoder, VHDL Code for 2 to 4 Decoder, Demultiplexer, ROM (Read Only Memory), Code Converter Seven Segment Display and Decoder, Encoder, Binary Encoder, Priority Encoder, VHDL Code for Combinational Circuits, Summary, Review Questions.
    3. Sequencial Circuits
    Objectives, Introduction, Sequential Circuits, NAND Latch, S–R Flip-Flop, D Flip-Flop, J-K Flip-Flop, Edge Triggered S–R Flip-Flop, PRESET and CLEAR Inputs, Shift Register, Binary Counter, Serial or Asynchronous Counter (Ripple Counter), BCD Counter (Mod-10 Counter/Decade Counter), Synchronous Counter (Parallel Counter), VHDL Code for Flip-Flops, Registers and Counters, VHDL Code for D-Latch, VHDL Code for D Flip-Flop, VHDL Code for J-K Flip-Flop, VHDL Code for Register, VHDL Code for Shift Register, VHDL Code for Counter, VHDL Code for R-S Flip-Flop, Summary, Review Questions.
    4. Synchronous/Asynchronous Sequencial Circuits
    Objectives, Introduction, Synchronous Sequential Circuits, Asynchronous Sequential Circuit, Finite-State Machine, FSM with Moore Machines, FSM with Mealy Machines, Equivalence of Mealy and Moore Machines, VHDL Code for FSM, Serial Adder, VHDL Code for Serial Adder, Vending Machine, A Simple Vending Machine, Understanding Basic Vending Machine, Abstract Representations, State Minimization, VHDL Code for Vending Machine, Vending Machine with VHDL, Summary, Review Questions.
    5. Digital System Design
    Objectives, Introduction, Building Block Circuits, Aims and Objectives, System Level Design, Computer Organization, Early Memory, Organization of Memory Device, Interfacing Memory to a Processor, Memory Terminology, Random Access Memory, Read Only Memory, Static RAM versus Dynamic RAM, Static RAM (SRAM), Dynamic RAM (DRAM), DRAM Organization, DRAM Timing, Clock Synchronization, Single Phase Clock, Two Phase Clock, 4-Phase Clock, Four Phase CCD Clocking, Clock Multiplier, Uses of Synchronization, Design Example of VHDL Writing to Standard Output, Simple Parallel 8-Bit sqrt using One Component, Optimized Parallel 8-Bit sqrt using Many Components, A Group of VHDL Components using Generic Parameters, A Serial Multiplier using Generic Components, Example of Behavioral and Circuit VHDL Barrel Shifter, Example of Serial Multiplier Model, Example of Serial Divider Model, Example of Parallel 32-bit Multiplier Model, Example of Parallel 4-Bit Divider Model, Example of Sorting Operation, CPU Organization, Computer Performance Measures: Program Execution Time, Hierarchy of Computer Architecture, CPU Execution Time: The CPU Equation, Aspects of CPU Execution Time, Computation and Control in CPU, Sorting Operation, Summary, Review Questions.
    A. Appendix
    P. Papers

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07 Sep 2013

selective topics

this book contain all topics according to rtu syllabus does not contain extra topics

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